406 tm HIP1013 low cost dual power distribution controller the HIP1013 is a low cost hot swap dual supply power distribution controller. two external n-channel mosfets are driven to distribute power while providing load fault isolation. at turn-on, the gate of each external n-channel mosfet is charged with a 10 a current source. capacitors on each gate (see the typical application diagram), create a programmable ramp (soft turn-on) to control inrush currents. a built in charge pump supplies the gate drive for the 12v supply n-channel mosfet switch. over current protection is facilitated by two external current sense resistors. when the current through either resistor exceeds the user programmed value the n-channel mosfets are latched off by the HIP1013. the controller is reset by a rising edge on either pwron pin. choosing the voltage selection mode the HIP1013 controls either +12v/5v or +3.3v/+5v supplies. although pin compatible with the hip1012 device, the HIP1013 does not offer current regulation during an oc event. features ? hot swap dual power distribution control for +5v and +12v or +5v and +3.3v ? provides fault isolation ? charge pump allows the use of n-channel mosfets ? redundant power on controls ? power good and over current latch indicators ? adjustable turn-on ramp ? protection during turn-on applications ? power distribution control ? hot plug? components pinout HIP1013 (soic) top view typical application diagram ordering information part number temp. range ( o c) package pkg. no. HIP1013cb -0 to 70 14 ld soic m14.15 HIP1013cb-t -0 to 70 14 ld soic tape and reel m14.15 3/12vs 3/12vg v dd pwron2 5vg 5vs 3/12visen gnd c pump nc r ilim pgood 5visen mode / pwron1 1 2 3 4 5 6 7 14 13 12 11 10 9 8 3/12vs 3/12vg pwron2 pgood 5vg 5vs 3/12visen gnd nc r ilim c pump 5isen v dd HIP1013 12v r load r ilim c pump r sense 5v r load r sense 5v v dd c gate c gate m/pon1 power on inputs data sheet may 1999 fn4516.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved hot plug? is a trademark of core international, inc.
407 functional diagram v dd 12vg 12vs 12isen 5vg 5vs 5isen gnd mode/ pgood r ilim c pump pwron2 qpump 100 a rising v dd r r s qn q por 10 a edge reset c pump r ilim 12v to load to load 12vin 5vin HIP1013 c gate c gate to v dd + - r sense pgood enable 10 a 18v + - 12v r sense nc pwron1 oc oc 12v 18v HIP1013
408 pin description pin no. symbol function description 1 12vs 12v source connect to source of associated external n-channel mosfet switch to sense output voltage. 2 12vg 12v gate connect to the gate of associated n-channel mosfet switch. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to 17.4v by a 10 a current source when in 5v/12v mode of operation, otherwise capacitor will be charged to 11.4v. 3v dd chip supply connect to 12v supply. this can be either connected directly to the +12v rail supplying the load voltage or to a dedicated v dd +12v supply. 4 mode/ pwron1 power on/ reset invokes 3.3v operation when shorted to v dd , pin 3. pwron1 and pwron2 are used to turn-on and reset the chip. both outputs turn-on when either pin is driven low. after an over current limit fault, the chip is reset by the rising edge of a reset signal applied to either pwron pin. each input has 100 a pull up capability which is compatible with 3v and 5v open drain and standard logic. pwron1 is also used to invoke 3.3v control operation in preference to +12v control. by tying pin 4 to pin 3 the charge pump is disabled and the uv threshold also shifts to 2.8v. 5pwron2 power on/reset 6 5vg 5v gate connect to the gate of the external 5v n-channel mosfet. a capacitor from this node to ground sets the turn-on ramp. at turn-on this capacitor will be charged to 11.4v by a 10 a current source. 7 5vs 5v source connect to the source side of 5v external n-channel mosfet switch to sense output voltage. 8 5visen 5v current sense connect to the load side of the 5v sense resistor to measure the voltage drop across this resistor between 5vs and 5visen pins. 9 pgood power good indicator pgood is driven by an open drain n-channel mosfet. it is pulled low when either output voltage is not within specification or and oc condition exists. 10 no connection. 11 c pump charge pump capacitor connect a 0.1 f capacitor between this pin and v dd (pin 3). 12 gnd chip ground 13 r ilim current limit set resistor a resistor connected between this pin and ground determines the current level at which current limit is activated. this current is determined by the ratio of the r ilim resistor to the sense resistor (r sense ). the current at current limit onset is equal to 10 ax(r ilim /r sense ). 14 12visen 12v current sense connect to the load side of sense resistor to measure the voltage drop across this resistor. HIP1013
409 absolute maximum ratings t a =25 o c thermal information v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +13.2v 3/12vg, c pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 18.5v 3/12visen, 3/12vs . . . . . . . . . . . . . . . . . . . . . . . -5v to v dd + 0.3v 5visen, 5vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5v to 7.5v pgood, r ilim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7.5v mode/pwron1 , pwron2 , 5vg . . . . . . . . . . -0.3v to v dd + 0.3v esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kv (class 2) operating conditions v dd supply voltage range . . . . . . . . . . . . . . . . . . +10.5v to +13.2v temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 70 o c thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 maximum junction temperature (plastic package) . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on an evaluation pc board in free air. 2. all voltages are relative to gnd, unless otherwise specified. electrical specifications v dd = 12v, c vg = 0.01 f, r sense = 0.1 ? , c bulk = 220 f, esr = 0.5 ? , t a = t j = 0 o c to 70 o c, unless otherwise specified parameter symbol test conditions min typ max units control section current limit threshold voltage (voltage across sense resistor) v il r ilim = 10k ? 85 100 115 mv over current limit response time oc lrt current overload, r ilim = 10k ? , r short = 6.0 ? -2- s response time to dead short rt short c vg = 0.01 f - 500 1000 ns 12v gate turn-on time t on12v c vg = 0.01 f-12-ms 5v gate turn-on time t on5v c vg = 0.01 f-5-ms gate turn-on current i on c vg = 0.01 f81012 a 12v under voltage threshold 12v vuv 10.5 10.8 11.0 v 5v under voltage threshold 5v vuv 4.35 4.5 4.65 v 3.3v under voltage threshold 3.3v vuv 2.65 2.8 2.95 v charge pumped 12vg voltage v12vg c pump = 0.1 f 16.817.317.9 v 3/5vg high voltage 3/5vg 11.2 11.9 - v supply current and io specifications v dd supply current i vdd 4810ma v dd por rising threshold por rvth 9.5 10.0 10.5 v v dd por falling threshold por fvth 9.3 9.8 10.3 v pwron pull-up voltage pwrn_v pwron pins open 1.8 2.4 3.2 v pwron rising threshold pwr_vth 1.1 1.5 2 v pwron hysteresis pwr_hys 0.1 0.2 0.3 v pwron pull-up current pwrn_i 60 80 100 a r ilim pin current source output r ilim _io 90 100 110 a charge pump output current qpmp_io c pump = 0.1 f, c pump = 16v 400 590 800 a charge pump output voltage qpmp_vo no load 17.2 17.4 - v charge pump output voltage - loaded qpmp_vio load current = 100 a16.216.7-v charge pump por rising threshold qpmp+vth 15.6 16 16.5 v charge pump por falling threshold qpmp-vth 15.2 15.7 16.2 v HIP1013
410 typical performance curves figure 1. supply current figure 2. r ilim source current figure 3. 12v uv threshold figure 4. 3.3v/5v uv threshold figure 5. 12v, 5v gate drive figure 6. charge pump voltage 8.2 8.0 7.8 7.6 7.4 7.2 -40 -20 0 20 40 60 80 temperature ( o c) 8.4 supply current(ma) -30 -10 10 30 50 70 104 103 -40 -20 0 20 40 60 80 102 70 50 30 10 -10 -30 105 temperature ( o c) current ( a) temperature ( o c) 12v uv threshold (v) 20 40 60 80 -40 -20 0 11.00 10.98 10.96 10.94 3.3v uv 20 40 60 80 -40 -20 0 4.615 4.610 4.605 4.600 4.595 2.888 2.886 2.884 2.882 2.880 temperature ( o c) 5v uv threshold (v) 3.3v uv threshold (v) 5v uv 12v vg 5v vg 20 40 60 80 -40 0 -20 17.36 17.34 17.32 17.30 17.28 17.26 11.935 11.930 11.925 11.920 11.915 11.910 11.905 11.900 temperature ( o c) 3.3v, 5v gate drive (v) 12v gate drive (v) 20 40 60 80 -40 0 -20 voltage (v) temperature ( o c) 17.6 17.4 17.2 16.8 16.6 17.0 charge pump voltage no load charge pump voltage 100 a load HIP1013
411 HIP1013 description and operation the HIP1013 offers the designer a cost efficient 5v and 12v true hot plug controller. this device drives two external n-channel mosfet switches and uses a charge pump to provide 17v to drive the gate of the 12v supply switch. the HIP1013 features over current (oc) programing with a single external resistor, r ilim and during turn-on, the gate capacitor of each external n-channel mosfet is charged with a 10 a current source. these capacitors create a programmable ramp (soft turn-on). upon initial power up, the HIP1013 can either isolate the voltage supply from the load by holding the external n-channel mosfet switches off or apply the supply rail voltage directly to the load for true hot swap capability. in either case the HIP1013 turns on in a soft start mode protecting the supply rail from sudden current loading. the load currents pass through two external current sense resistors. when the voltage across either resistor exceeds the user programmed over current (oc) voltage threshold value, (see table 1) the HIP1013 controller turns both n-channel mosfets off in 2 s. the HIP1013 is reset by a rising edge on either pwron pin and is turned on by either pwron pin being driven low. the HIP1013 can control either +12v/5v or +3.3v/+5v supplies. tying the pwron1 pin to v dd , invokes the +3.3v/+5v voltage mode. in this mode, the external charge pump capacitor is not needed and c pump , pin 11 is also tied directly to v dd . upon any oc or under voltage (uv) condition the pgood fault indicating signal will pull low when tied high through a resistor to the logic supply. figure 7. oc voltage threshold with = r ilim 10k ? figure 8. power on reset voltage threshold typical performance curves (continued) 20 40 60 80 -40 0 -20 voltage threshold (mv) 12 oc vtth 5 oc vth temperature ( o c) 102.5 102.0 101.5 101.0 100.5 -40 -20 0 20 40 60 80 -30 -10 10 30 50 70 10.2 10.0 9.8 9.6 power on reset (v) temperature ( o c) v dd low to high v dd high to low table 1. r ilim resistor nominal oc vth 15k 150mv 10k 100mv 7.5k 75mv 4.99k 50mv note: nominal oc vth = r ilim x 10 a HIP1013
412 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 HIP1013 application considerations there is no unique and specific HIP1013 application evaluation board . since the HIP1013 is pin compatible with the hip1012 device, you can substitute a HIP1013 for the existing hip1012 in either of the hip1012eval1 or eval2 boards. otherwise contact your intersil corporation sales office and an already modified board will be provided. although pin compatible to the hip1012, the HIP1013 is a less featured dual power supply distribution controller and does not include programmable current limiting regulation and delay time to latch off. random resets can also occur if the HIP1013 (pins 8 and 14) sense pins are pulled below ground when turning off a highly inductive load. place a large load capacitor (10-50 f) on the output to eliminate unintended resets. physical layout of r sense resistors is critical to avoid the possibility of false over current occurrences. ideally trace routing between the r sense resistors and the HIP1013 vs and visen pins are direct and as short as possible with zero current in the sense lines. correct incorrect to HIP1013 vs and visen to HIP1013 vs and visen current sense resistor HIP1013
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